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tm 3-1 HSP43216 halfband filter the HSP43216 halfband filter addresses a wide variety of applications by combining f s /4 (f s = sample frequency) quadrature up/down convert circuitry with a ?ed coef?ient halfband ?ter processor as shown in the block diagram. these elements may be con?ured to operate in one of the four following modes: decimate by 2 ?tering of a real input signal; interpolate by 2 ?tering of a real input signal; f s /4 quadrature down conversion of a real input signal followed by decimate-by-2 ?tering to produce a complex analytic signal; interpolate-by-2 ?tering of a complex analytic signal followed by f s /4 quadrature up conversion to produce a real valued output. the frequency response of the HSP43216's halfband ?ter has a shape factor, (passband+transition band)/passband, of 1.24:1 with 90db of stopband attenuation. the passband has less than 0.0003db of ripple from 0f s to 0.2f s with stopband attenuation of greater than 90db from 0.3f s to nyquist. at 0.25f s the ?ter provides 6db of attenuation. the HSP43216 processes data streams with word widths up to 16 bits and data rates up to 52 msps. the processing throughput of the part is easily doubled to rates of up to 104 msps by using the part together with an external multiplexer or demultiplexer. programmable rounding is provided to support output precisions from 8 bits to 16 bits. features sample rates to 52 msps architected to support sample rates to 104 msps using external multiplexer four modes of operation: - interpolate by 2 filtering - decimate by 2 filtering - quadrature to real signal conversion -f s /4 quadrature down conversion followed by decimate by 2 filtering 16-bit inputs and outputs 67-tap halfband fir filter with 20-bit coef?ients twos complement or offset binary outputs programmable rounding on outputs 1.24:1 filter shape factor >90db stopband attenuation <0.0003db passband ripple saturation logic on output applications digital down conversion d/a and a/d pre/post filtering tuning bandwidth expansion for hsp45116 and hsp45106 block diagram ordering information part number temp. range ( o c) package type pkg. no. HSP43216jc-52 0 to 70 84 ld plcc n84.1.15 HSP43216vc-52 0 to 70 100 ld mqfp q100.14x20 input data flow controller f s /4 quadrature processor 67-tap processor f s /4 quadrature up convert processor output data flow controller/ formatter ain0-15 bin0-15 aout0-15 bout0-15 mode0-1 sync usb/lsb int/ext rnd0-2 fmt down convert halfband filter oea oeb clk data sheet september 2000 file number 3365.8 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
3-2 pinouts 100 lead mqfp top view 99 98 97 96 95 94 93 91 89 87 85 84 83 81 82 86 88 90 92 100 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 40 42 44 46 47 48 50 49 45 43 41 39 31 v cc nc nc nc nc sync usb/lsb int/ext bin0 bin1 bin2 bin3 bin4 bin5 bin6 bin7 bin8 bin9 bin10 bin11 bin12 bin13 bin14 bin15 rnd0 rnd1 nc nc nc nc bout14 bout13 bout12 bout11 bout10 gnd bout9 bout8 bout7 bout6 bout5 bout4 bout3 bout2 bout1 bout0 v cc gnd oeb rnd2 v cc fmt oea gnd aout15 aout14 aout13 aout12 aout11 aout10 aout9 aout8 aout7 aout6 aout5 aout4 aout3 aout2 aout1 aout0 gnd nc nc nc nc bout15 nc nc nc nc ain0 ain1 ain2 ain3 ain4 ain9 ain8 ain7 ain6 ain5 ain15 ain14 ain13 ain12 ain11 ain10 gnd mode1 mode0 clk HSP43216
3-3 84 lead plcc top view pinouts (continued) ain0 ain1 ain2 ain3 ain4 ain9 ain8 ain7 ain6 ain5 ain15 ain14 ain13 ain12 ain11 ain10 gnd mode1 mode0 bout15 bout14 bout13 bout12 bout11 bout10 gnd bout9 bout8 bout7 bout6 bout5 bout4 bout3 bout2 bout1 bout0 v cc gnd oeb rnd2 sync usb/lsb int/ext bin0 bin1 bin2 bin3 bin4 bin5 bin6 bin7 bin8 bin9 bin10 bin11 bin12 bin13 bin14 bin15 rnd0 rnd1 v cc fmt oea gnd aout15 aout14 aout13 aout12 aout11 aout10 aout9 aout8 aout7 aout6 aout5 aout4 aout3 aout2 aout1 aout0 gnd v cc clk 111098765432184838281807978777675 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 pin description name type description v cc - +5v power. gnd - ground. clk i clock input. (cmos level). f s is the frequency of clk ain0-15 i input data bus a. ain0 is the lsb. input data format is 16-bit twos complement. bin0-15 i input data bus b. bin0 is the lsb. input data format is 16-bit twos complement. mode0-1 i the mode select inputs set one of four operational modes as highlighted in table 1. int/ext i the internal\external multiplexer select inputs set whether the data multiplex/demultiplex function required in the various operational modes is performed internally (high state) or externally to the chip (low state). sync i this input is used to synchronize the input sample stream with the zero degree phase of the up or down convert local oscillators. in the straight decimate modes, this input can be use to synchronize the input sample stream with a particular phase of the halfband ?ter. (see the operational modes section for additional information). usb/lsb i the upper and lower sideband select line is used to specify the direction of frequency translation imparted on the data stream in the down convert and decimate mode and in the quadrature to real convert mode. (see operational modes section for additional information). rnd0-2 i the round select inputs set the number of output bits from eight (rnd = 000) to sixteen (rnd = 110). least signi?ant output bits are zeroed. see table 4. oea i three-state control output bus a, outa0-15. active low. oeb i three-state control output bus b, outb0-15. active low. fmt i the format select input is used to convert the twos complement output to offset binary (unsigned). when asserted high, the aout15 and bout15 bits are inverted from the normal twos complement representation. aout0-15 o output bus a. aout0 is the lsb. bout0-15 o output bus b. bout0 is the lsb. HSP43216
3-4 functional description the operation of the HSP43216 centers around a ?ed coef?ient, 67-tap, halfband filter processor as shown in figure 1. the halfband filter processor operates stand alone to provide two fundamental modes of operation: interpolate or decimate by two ?tering of a real signal. in two other modes, the quadrature up/down convert circuitry operates together with the filter processor block to provide f s /4 down conversion with decimate by 2 ?tering or quadrature to real conversion. in down convert and decimate mode, a real input sample stream is spectrally shifted by f s /4. each component of the resulting complex signal is then halfband ?tered and decimated by 2 to produce real and imaginary output samples at half of the input data rate. in quadrature to real conversion mode, the real and imaginary components of a quadrature input are interpolated by two and halfband ?tered. the ?tered result is then spectrally shifted by f s /4 and the real component of this operation is output at twice the input sample rate.the HSP43216 is con?ured for different operational modes by setting the state of the mode control pins, mode1-0 as shown in table 1. input data flow controller the input data flow controller routes data samples from the ain0-15 and bin0-15 inputs to the internal processing elements of the halfband. the data routing paths are based on mode of operation and are more fully discussed in the operational modes section. f s /4 quadrature down convert processor the f s /4 quadrature down convert processor operates as a quadrature lo which provides the negative f s /4 spectral shift required to center the upper sideband of a real input signal at dc. this operation is equivalent to multiplying the real sample stream, x(n), by the quadrature components of the complex exponential e -j( /2)n as given below: r e g m u x f s /4 l.o. mux mux 1,-1,1,.. -1,1,-1,. 1 1 even tap filter mux mux 1 1 ...,2,-2,2 ..,-2,2,-2 m u x odd tap filter ain0-15 bin0-15 bout0-15 aout0-15 oea oeb usb/lsb r e g r e g r e g r e g r e g r e g r e g r e g r n d f m t r e g r e g r n d f m t r e g r e g r e g r e g 2 2 ? indicates elements which operate at clk/2 when the int/ext control input is high. sync int/ext rnd0-2 fmt mode0-1 input data flow controller f s /4 quadrature down convert 67-tap halfband filter f s /4 quadrature up convert output data flow controller processor processor ? delay 19 ? delay 2 - 35 sync processor ? ? ? ? ? + ? figure 1. halfband block diagram clk usb/lsb pipeline pipeline table 1. mode select table mode1-0 mode 00 decimate by two 01 interpolate by two 10 down convert and decimate 11 quadrature to real conversion xn () e j n2 ? () xn () n2 ? () jx n () n2 ? () sin + cos = (eq. 1) HSP43216
3-5 for added ?xibility, a spectrally reversed version of the above process may be realized by con?uring the down convert processor to impart a positive f s /4 spectral shift on the input signal. this has the effect of centering the lower sideband of the input signal at dc and is achieved by reversing the sign of the sine term in the quadrature mix as shown below: the direction of the spectral shift imparted by the down convert processor is set by the upper sideband/ lower sideband control input, usb/lsb. when this input is high, a -f s /4 spectral shift is used to center the input signals upper sideband at dc. when asserted low, a spectral shift of f s /4 is used to center the lower sideband at dc. the sync control input may be used to synchronize the incoming data stream with the zero degree phase of the complex exponential as described in the operational modes section. the real and imaginary sample streams generated by the down convert operation are passed to the halfband filter block on the upper and lower processing legs respectively. the down convert processor is only active in down convert and decimate mode, mode1-0 = 10. in the other modes, the data on the upper and lower processing legs pass unaltered. 67-tap halfband filter processor the processing required to implement the 67-tap halfband ?ter is distributed across two polyphase branches comprised of even and odd tap ?ters as shown in figure 1. the even tap filter performs a ?tering operation using the even indexed coef?ients (even phase) of the halfband ?ter. the odd tap filter uses the odd indexed coef?ients (odd phase) of the halfband ?ter. note: the odd tap ?ters processing reduces to a delay and scale operation since the center tap is the only non-zero odd tap for a halfband ?ter. together the polyphase ?ters perform the sum of-products required to implement the 67-tap halfband ?ter in an architecture capable of supporting a variety of operational modes. the frequency response of the halfband ?ter is given graphically in figure 2 and in tabular form in table 3. table 2 shows the different modes and the related frequency with which the spectra in figure 2 is normalized. the polyphase implementation of the halfband filter provides the flexibility to realize a variety of filter configurations. in decimate by two mode, the outputs of the each polyphase branch are summed to yield the filter output. in interpolate by two mode, the polyphase filters produce independent outputs which are multiplexed into a single sample stream at the interpolated data rate. in the up convert and down convert modes, the polyphase branches filter the real and imaginary components of a complex sample stream with the equivalent of identical 67- tap halfband filters. for these modes, the real component is processed by the even tap filter and the imaginary component is processed by the odd tap filter. the operational modes section provides further details regarding the data flow and operation of the filter processor for the various modes. as a standard dsp term, group delay is de?ed as the time it takes to obtain valid ?tered data given a certain input pattern. both the even tap and odd tap ?ters have an identical group delay of 19 clocks relative to the operating mode of the halfband. the group delay has been speci?d in the data ?w diagrams following this section. the delay clocks equal clk when int/ext = 0 and clk/2 when int/ext = 1. note: pipeline delay speci?s the time it takes for bits to toggle at the output given a certain input pattern. the odd tap ?ter has a pipeline delay of 19 clks with respect to the operating mode because it consists of only the center tap of the 67-tap halfband. the even tap filter has a pipeline delay of 2-35 clks with respect to the operating mode. table 2. normalized freqruency vs mode mode f s decimate by two clk interpolate by two clk/2 down convert and decimate clk quadrature to real clk/2 xn () e j n2 ? () x n () n2 ? () jx n () n2 ? () sin + cos = (eq. 2) 0 -20 -40 -60 -80 -100 -120 0f s /4 f s /2 magnitude (db) normalized frequency 3f s /8 f s /8 figure 2. frequency response of 67-tap halfband filter HSP43216
3-6 table 3. frequency response of the 67-tap halfband filter normalized to the mode specific sample rate quency malized) magnitude (db) frequency (normalized) magnitude (db) frequency (normalized) magnitude (db) frequency (normalized) magnitu (db) 000000 -0.000256 0.125000 -0.000278 0.250000 -6.020594 0.375000 -90.46953 003906 -0.000143 0.128906 -0.000098 0.253906 -7.989334 0.378906 -91.52873 007812 -0.000071 0.132812 0.000001 0.257812 -10.364986 0.382812 -98.96020 011719 -0.000013 0.136719 0.000077 0.261719 -13.194719 0.386719 -105.2350 015625 -0.000004 0.140625 0.000166 0.265625 -16.533196 0.390625 -97.07321 019531 -0.000001 0.144531 0.000106 0.269531 -20.447622 0.394531 -101.7908 023438 0.000032 0.148438 0.000015 0.273438 -25.024382 0.398438 -103.6605 027344 -0.000000 0.152344 -0.000022 0.277344 -30.379687 0.402344 -96.90327 031250 -0.000026 0.156250 -0.000048 0.281250 -36.679477 0.406250 -97.16086 035156 0.000002 0.160156 -0.000074 0.285156 -44.169450 0.410156 -106.8046 039062 0.000036 0.164062 -0.000022 0.289062 -53.259353 0.414062 -96.21376 042969 0.000050 0.167969 0.000005 0.292969 -64.619008 0.417969 -91.36835 046875 0.000021 0.171875 0.000009 0.296875 -79.291213 0.421875 -91.20296 050781 0.000008 0.175781 0.000041 0.300781 -90.247748 0.425781 -96.90327 054688 -0.000012 0.179688 0.000095 0.304688 -91.540418 0.429688 -103.0587 058594 -0.000140 0.183594 0.000090 0.308594 -96.987389 0.433594 -92.15650 062500 -0.000226 0.187500 -0.000012 0.312500 -97.990997 0.437500 -90.24774 066406 -0.000138 0.191406 -0.000037 0.316406 -94.450644 0.441406 -91.62316 070312 0.000010 0.195312 -0.000145 0.320312 -94.268681 0.445312 -98.76039 074219 0.000036 0.199219 -0.000208 0.324219 -97.250387 0.449219 -103.8832 078125 0.000179 0.203125 -0.000927 0.328125 -103.660592 0.453125 -96.86183 082031 0.000190 0.207031 -0.005089 0.332031 -105.940671 0.457031 -96.98738 085938 0.000064 0.210938 -0.018871 0.335938 -98.212931 0.460938 -100.0465 089844 0.000011 0.214844 -0.053894 0.339844 -94.313447 0.464844 -106.8046 093750 -0.000064 0.218750 -0.128250 0.343750 -95.354251 0.468750 -104.1190 097656 -0.000018 0.222656 -0.266964 0.347656 -98.447393 0.472656 -105.2350 101562 -0.000000 0.226562 -0.501238 0.351562 -103.249457 0.476562 -104.6376 105469 0.000020 0.230469 -0.866791 0.355469 -93.387604 0.480469 -105.9406 109375 0.000053 0.234375 -1.401949 0.359375 -91.390894 0.484375 -107.3230 113281 0.000012 0.238281 -2.145948 0.363281 -94.404415 0.488281 -102.3752 117188 -0.000022 0.242188 -3.137997 0.367188 -103.883234 0.492188 -94.0096 121094 -0.000149 0.246094 -4.416657 0.371094 -93.245384 0.496094 -91.3125 HSP43216
3-7 f s /4 quadrature up convert processor the f s /4 quadrature up convert processor provides the f s /4 spectral shift used to construct a real signal from a complex sample stream. the operation performed is equivalent to multiplying a quadrature data stream, i(n)+jq(n), by samples of a complex exponential, e -j( /2)n , and outputting the real part of that mathematical operation as given below: real { (i (n) + jq(n) ) e j ( n/2) } = real {[i (n) cos ( n/2) - q(n) sin ( n/2)] + j [i (n) sin ( n/2) + q(n) cos ( n/2)]} = i (n) cos ( n/2) - q(n) sin ( n/2) = i (n) cos ( n/2) + q(n) sin ( ? n/2) (eq. 3) in the above operation, a positive f s /4 spectral shift is imparted on the quadrature input which causes the upper sideband of the resulting real output to be de?ed by the spectral content of the input signal as shown in figure 3. for added ?xibility, the up convert processor may be con?ured to impart a negative f s /4 shift on the quadrature input which generates a real output whose lower sideband is de?ed the spectrum of the quadrature input as shown in figure 4. the state of the usb/lsb control input determines the direction of the spectral shift. if this input is set ?igh? a positive f s /4 shift is introduced by the up convert processor. if usb/lsb is asserted ?ow? a negative f s /4 spectral shift is introduced. the up convert processor implements the up convert operation by multiplying the in-phase and quadrature samples on the upper and lower processing legs by the nonzero sine and cosine terms in the above expression. the resulting data is then multiplexed together in the output flow controller to yield the real output sample stream. the sync control input may be used to align the zero degree phase of the up convert lo with a particular input sample as described in the operational modes section. the up convert processor also scales the data streams output from the filter processor as required by the operational mode. in the modes which employ interpolation, the up convert processor scales the filter processors output by two to compensate for the attenuation of one half caused by the interpolation process. in down convert and decimate mode, the ?ter processor output is also scaled by two to compensate for the attenuation introduced by the down covert process. the scaling operations performed are summarized in table 4. output data flow controller the output flow controller routes data to the aout0-15 and bout0-15 output depending on mode of operation. in decimate by two mode (mode1-0 = 00), output from the ?ter processors polyphase branches are summed and output through aout0-15. in down convert and decimate mode (mode1-0 = 10), real and imaginary data streams produced by the down convert process pass are output directly to aout0-15 and bout0-15 respectively. in the two modes using interpolation, mode1-0 = 01 or 11, with internal multiplexing enabled, int/ext set high, data sam ples output from the polyphase branches are internally multiplexed into a single stream and output via aout0-15. if a mode using interpolation is speci?d together with external multiplexing, int/ext set low, the data stream multiplexing is performed off chip and the data on the upper and lower processing legs is output through aout0-15 and bout0-15. the output data flow controller also sets the binary format and precision of the two 16-bit outputs. the data format is speci?d as either twos complement (fmt input low) or offset binary (fmt input high). the precision of the output data is set from 8 to 16 bits via the round control inputs, rnd2-0. the rnd2-0 inputs round the output data to a precision ranging from 8 to 16 bits as speci?d in table 5. saturation logic is incorporated in the output ?w controller to insure that numerical growth associated with a worst case signal input or rounding condition saturates to a 16-bit value. figure 3. f s /4 positive shift: up conversion figure 4. f s /4 negative shift: down conversion 0f s /4 -f s /4 -f s /2 f s /2 0f s /4 -f s /4 -f s /2 f s /2 0f s /4 -f s /4 -f s /2 f s /2 0f s /4 -f s /4 -f s /2 f s /2 table 4. scale factors applied by up convert processor vs mode mode scale factor decimate by two (mode1-0 = 00) 1.0 interpolate by two (mode1-0 = 01) 2.0 down convert and decimate (mode1-0 = 10) 2.0 quadrature to real (mode1-0 = 11) 2.0 HSP43216
3-8 operational modes decimate by 2 filter mode (mode1-0 = 00) the concept of operation for decimate by two filter mode is most easily understood by comparing the 7 tap transversal ?ter implementation to the equivalent polyphase implementation. the transversal implementation is shown in figure 5. by inspecting the sum-of-products for the decimated output in figure 5, it is seen that even indexed input samples are always multiplied by the even ?ter coef?ients and the odd samples are always multiplied by the odd coef?ients. this computational partitioning is realized in the polyphase implementation shown in figure 6. in the polyphase implementation, the input data is broken into even and odd sample streams which are processed by a set of polyphase filters running at one half of the input data rate. these filters are designated as even or odd tap filters depending upon whether the coefficients were derived from the even or odd indexed coefficients of the original transversal filter. this architecture only produces the outputs which are not discarded by the decimation process. note: since the only non-zero tap for a halfband filter is the center tap, the odd tap filter reduces to a delay and multiply operation. the operation of the HSP43216 in decimate by two mode is analogous to the polyphase implementation in figure 6. in this mode, the internal data paths are routed as shown in figure 7a and figure 7b. the different data ?ws depend on whether internal or external multiplexing has been selected using the int/ext control input. in either case, an input data stream is decomposed into even and odd sample streams which are then routed to the even and odd tap polyphase ?ters. the output of each polyphase ?ter is summed and output via aout0-15. table 5. output rounding control rnd 2-0 round function 000 round output to 8 bits, aout15-8 and bout15-8, zero lower bits. 001 round output to 9 bits, aout15-7 and bout15-7, zero lower bits. 010 round output to 10 bits, aout15-6 and bout15-6, zero lower bits. 011 round output to 11 bits, aout15-5 and bout15-5, zero lower bits. 100 round output to 12 bits, aout15-4 and bout15-4, zero lower bits. 101 round output to 14 bits, aout15-2 and bout15-2, zero lower bits. 110 round output to 16 bits, aout15-0 and bout15-0. 111 zero all outputs. c0 c1 c2 c3 c4 c5 c6 x3,x2,x1,x0 y(0) = x0(c0)+x1(c1)+x2(c2)+x3(c3)+x4(c4)+x5(c5)+x6(c6) y(1) = x1(c0)+x2(c1)+x3(c2)+x4(c3)+x5(c4)+x6(c5)+x7(c6) y(2) = x2(c0)+x3(c1)+x4(c2)+x5(c3)+x6(c4)+x7(c5)+x8(c6) y(3) = x3(c0)+x4(c1)+x5(c2)+x6(c3)+x7(c4)+x8(c5)+x9(c6) ...,y1,y0 2 ..,y4,y2,y0 ? indicates samples discarded by decimation process ? ? figure 5. transversal implementation of deci- mate by 2 halfband filter c0 c2 c4 c6 ...,x4,x2,x0 y(0) = x0(c0)+x1(c1)+x2(c2)+x3(c3)+x4(c4)+x5(c5)+x6(c6) y(1) = x2(c0)+x3(c1)+x4(c2)+x5(c3)+x6(c4)+x7(c5)+x8(c6) ..,y2,y1,y0 c1 c3 c5 r e g odd tap filter even tap filter ...,x5,x3,x1 + figure 6. polyphase implementation of decimate by 2 halfband filter HSP43216
3-9 if internal multiplexing is selected ( int/ext = 1), the input data stream is decomposed into even and odd samples internally by the processing elements operating at one half of the input clk (see elements marked by ? ?in figure 7a). in this mode, the data flow controller routes data samples input through ain0- 15 to upper and lower processing legs with a one sample relative delay. since a new data sample is clocked into either of the processing legs at clk/2, each leg processes a data stream comprised of every other input sample, and the one sample relative delay of each legs input forces the even samples to be clocked into one leg while the odd samples are clocked into the other. the user may choose which sample gets routed to the upper (even) processing leg by asserting sync. specifically, a sample input on the clk following the assertion of sync will be routed to the upper processing leg as shown in figure 8. with internal multiplexing, the minimum pipeline delay on the upper processing leg is 14 clks and the pipeline delay on the bottom leg is 47 clks. the filtered and decimated data stream is held on aout0-15 for 2 clks. if external multiplexing is selected ( int/ext = 0), a demultiplex function is required off chip to break the input data into even and odd sample streams for input through ain0-15 and bin0-15. in this mode, the data flow controller routes the even and odd sample streams directly to the following processing elements which are all running at the input clk rate. this allows the device to perform decimate by two ?tering on signals sampled at up to twice the maximum clk rate of the device (104 msps). with external multiplexing, the minimum pipeline delay through the upper processing leg is 9 clks and the pipeline delay through the lower processing leg is 26 clks as shown in figure 7b. in this mode, sync has no effect on part operation. note: for proper operation, the samples demultiplexed to the ain0-15 input must precede those input to the bin0-15 input in sample order. for example, given a data sequence x0, x1, x2 and x3, the demultiplex function would route x0 and x2 to ain0-15 and x1 and x3 to bin0-15. interpolate by 2 filter mode (mode1-0 = 01) as with the decimate by two mode the concept of operation for the interpolate by two filter mode is more easily understood by comparing a 7 tap transversal ?ter implementation to the equivalent polyphase implementation. the transversal implementation is shown in figure 9. by inspecting ?ter outputs in figure 9, it is seen that the even indexed outputs are the result of the sum-of-products for the odd coef?ients, and the odd indexed outputs are the result of the sum-of-products for the even coef?ients. this computational partitioning is evident in the polyphase implementation shown in figure 10. figure 7a. data flow diagram for decimate by 2 filter mode ( int/ext = 1) figure 7b. data flow diagram for decimate by 2 filter mode ( int/ext = 0) even tap filter odd tap filter ? group delay 19 ain0-15 aout0-15 oea r e g r e g r e g r e g r e g r e g r n d f m t r e g r e g r e g r e g 1 1 1 1 ? clocked at clk/2 ? group delay 19 ? + ? ? ? ?? ? pipeline delay 2-35 ? pipeline delay 19 even tap filter ain0-15 aout0-15 r e g r e g r e g r n d f m t r e g r e g r e g e g 1 1 r e g r e g r e g r e g r e g 1 odd tap filter oea 1 bin0-15 + group delay 19 pipeline delay 2-35 group delay 19 pipeline delay 19 r 012 clk sync inputs designated as even are processed on the upper leg, inputs designated as odd are processed on the lower leg. ain0-15 figure 8. data synchronization with processing legs ( int/ext = 1) even odd even HSP43216
3-10 in the polyphase implementation, the input data stream feeds even and odd tap ?ters running at the input sample rate. the interpolated sample stream is derived by multiplexing the output of each polyphase branch into a single data stream at twice the input sample rate. as in the decimate by two example, the even or odd tap ?ters are comprised of the even or odd indexed coef?ients from the original transversal ?ter. the operation of the HSP43216 in interpolate by two mode is analogous to the polyphase example above. in this mode the internal data ?w is routed as shown in figure 11a and figure 11b. the different data ?ws depend on the selection of internal or external multiplexing via int/ext. in this mode, data input through ain0-15 is fed to the even and odd polyphase branches of the ?ter processor. the output of each branch is multiplexed together to generate the output data stream at the interpolated rate. note: the output of each polyphase branch is scaled by two to compensate for the attenuation of one half caused by interpolation. c0 c1 c2 c3 c4 c5 c6 ..,x2,x1,x0 y(1) = x0(c0)+0(c1)+x1(c2)+0(c3)+x2(c4)+0(c5)+x3(c6) y(0) = 0(c0)+x0(c1)+0(c2)+x1(c3)+0(c4)+x2(c5)+0(c6) ...,y1,y0 2 ..x1,0,x0,0 7 tap halfband filter y(3) = x1(c0)+0(c1)+x2(c2)+0(c3)+x3(c4)+0(c5)+x4(c6) y(2) = 0(c0)+x1(c1)+0(c2)+x2(c3)+0(c4)+x3(c5)+0(c6) figure 9. transversal implementation of interpolate by two halfband filter c0 c2 c4 c6 ...,x2,x1,x0 y0 = x0(c1)+x1(c3)+x2(c5) y1 = x0(c0)+x1(c2)+x2(c4)+x3(c6) ..,y4,y2,y0 c1 c3 c5 r e g odd tap filter even tap filter m u x ..,y5,y3,y1 ..,y2,y1,y0 y2 = x1(c1)+x2(c3)+x3(c5) figure 10. polyphase implementation of interpolate by two halfband filter figure 11a. data flow diagram for interpolate by 2 filter mode ( int/ext = 1) figure 11b. data flow diagram for interpolate by 2 filter mode ( int/ext = 0) even tap filter odd tap filter ain0-15 aout0-15 oea r e g r e g r e g r e g r e g r e g r n d f m t r e g r e g r e g r e g 1 1 2 2 r e g m u x ? clocked at clk/2 ? ? ? ? ? ? ? group delay 19 ? group delay 19 ? pipeline delay 2-35 ? pipeline delay 19 even tap filter ain0-15 aout0-15 r e g r e g r e g r n d f m t r e g r e g r e g 1 1 r e g r e g 1 odd tap filter oeb 1 bout0-15 r n d f m t r e g r e g oea group delay 19 pipeline delay 2-35 group delay 19 pipeline delay 19 r e g r e g HSP43216
3-11 if internal multiplexing is selected (int/ext = 1), the data stream input through ain0-15 is fed to both the upper and lower processing legs as shown in figure 11a. the output of each processing leg is then multiplexed together to produce the interpolated sample stream at twice the input sample rate. in this mode the device is clocked at the interpolated data rate to support the multiplexing of each processing legs output into a single data stream. the upper and lower processing legs each run at the input data rate of clk/2 as indicated by the ? marking the various registers and processing elements in figure 11a. in this mode, data samples are clocked into the part on every other rising edge of clk. the sync signal is used to specify which set of clk cycles are used to register data at the parts input. specifically, every other rising edge of clk starting one clk after the assertion of sync will be used to clock data into the part. with internal multiplexing the minimum pipeline delay through the upper processing leg is 15 clks and the pipeline delay through the lower processing leg is 48 clks, (2[19+3]+4). if external multiplexing is selected ( int/ext = 0), the upper and lower processing legs are output through aout0-15 and bout0-15 for multiplexing into a single data stream off chip.this allows the processing legs to run at the maximum clock rate which coincides with an interpolated output data rate of 104 msps. note: the samples output on bout0-15 precede those on aout0-15 in sample order. this requires a multiplexing scenario in which bout0-15 is selected before aout0-15. with external multiplexing, the minimum pipeline delay through the upper processing leg is 9 clks and the pipeline delay through the lower processing leg is 26 clks as shown in figure 11b. in this mode sync has no effect on part operation. down convert and decimate mode (mode1-0 = 10) in down convert and decimate mode a real input signal is spectrally shifted -f s /4 which centers the upper sideband at dc. this operation produces real and imaginary components which are each filtered and decimated by identical 67-tap halfband filters. for added flexibility, a positive f s /4 spectral shift may be selected which centers the lower sideband at dc. the direction of the spectral shift is selected via usb/lsb as described in the quadrature down convert section. a spectral representation of the down convert and decimate operation is shown in figure 12 (usb/lsb = 1). note: each of the complex terms output by the filter processor are scaled by two to compensate for the attenuation of one half introduced by the down conversion process. the down convert and decimate mode is most easily understood by ?st considering the transversal implementation using a 7 tap ?ter as shown in figure 13. by examining the combination of down conversion, ?tering and decimation, it is seen that the real outputs are only dependent on the sum-of-products for the even indexed samples and ?ter coef?ients, and the imaginary outputs are only a function of the sum-of-products for the odd indexed samples and ?ter coef?ients. this computational partitioning allows the quadrature ?ters required after down conversion to be realized using the same poly-phase processing elements used in the previous two modes. a functional block diagram of the polyphase implementation is shown in figure 14. in this implementation, the input data stream is broken into even and odd sample streams and processed independently by the even and odd tap ?ters. by decomposing the sample stream into even and odd samples, the zero mix terms produced by the down convert lo drop out of the data streams, and the output of each of the ?ters represent the decimated data streams for both the real and imaginary outputs. input signal spectrum down converted signal filtered signal filter passband decimated output signal spectrum 0f s /2 f s -f s /2 0f s /2 f s -f s /2 0f s /2 f s -f s /2 0f s 2f ? -f s f s = input sample rate f s = decimated sample rate, f s /2 figure 12. down convert and decimate operation HSP43216
3-12 the HSP43216s implementation of down convert and decimate mode is analogous to the polyphase solution shown in figure 14. the parts data flow diagram for this mode is shown in figure 15a and figure 15b. as seen in the figures, the input sample data is broken into even and odd sample streams which feed the upper and lower processing legs as described in the decimate by 2 mode section. the data on each processing leg is then modulated with the nonzero quadrature components of the complex exponent (see quadrature down convert section). following this operation, the upper leg becomes the processing chain for the real (in-phase) component of the quadrature down conversion and the lower leg processes the complex (quadrature) component of the down conversion. the filter processing block implements the equivalent of a decimate by two halfband filter on each of the quadrature legs. if internal multiplexing is specified (int/ext = 1), the upper and lower processing legs are fed with even and odd sample streams which are derived from data input through ain0-15. the input sample stream may be synchronized with the zero degree phase term of the down converter lo by using the sync control input. for example, an input data sample will be fed into the real (upper) processing leg and mixed with the zero degree cosine term of the quadrature lo if it is input on the 4th clk following the assertion of sync as shown in figure 16. the pipeline delay through the real processing leg (upper leg) is 14 clks and the delay through the imaginary processing leg (lower leg) is 47 clks. the complex samples output through aout0-15 and bout0-15 are present for 2 clks since the quadrature streams have been decimated by two in the filter processor. c0 c1 c2 c3 c4 c5 c6 ...x2,x1,x0 ...,r2,r0 2 c0 c1 c2 c3 c4 c5 c6 1, 0,-1, 0... 0,-1,0,1... ...,i2,i0 real outputs r0 = x0(c0)+0(c1)-x2(c2)+0(c3)+x4(c4)+0(c5)-x6(c6) r1 = 0(c0)-x2(c1)+0(c2)+x4(c3)+0(c4)-x6(c5)+0(c6) r2 = -x2(c0)+0(c1)+x4(c2)+0(c3)-x6(c4)+0(c5)+x4(c6) r3 = 0(c0)+x4(c1)+0(c2)-x6(c3)+0(c4)+x4(c5)+0(c6) imaginary outputs i0 = 0(c0)-x1(c1)+0(c2)+x3(c3)+0(c4)-x5(c5)+0(c6) i1 = -x1(c0)+0(c1)+x3(c2)+0(c3)-x5(c4)+0(c5)+x7(c6) ? indicates samples discarded by decimation process i2 = 0(c0)+x3(c1)+0(c2)-x5(c3)+0(c4)+x7(c5)+0(c6) i3 = x3(c0)+0(c1)-x5(c2)+0(c3)+x7(c4)+0(c5)-x9(c6) halfband filter halfband filter 2 cos( n /2) sin(- n /2) ? ? ? ? figure 13. down convert and decimate function using transversal filters c0 c2 c4 c6 ...,x4,x2,x0 r0 = x0(c0)-x2(c2)+x4(c4)-x6(c6) r1 = -x2(c0)+x4(c2)-x6(c4)+x8(c6) c1 c3 c5 r e g odd tap filter even tap filter r2 = x4(c0)-x6(c2)+x8(c4)-x10(c6) 1,-1,1,-1,.. -1,1,-1,1.. cos lo sin lo ...,x5,x3,x1 ...,r1,r0 ...,i1,i0 real outputs i0 = -x1(c1)+x3(c3)-x5(c5) i1 = x3(c1)-x5(c3)+x7(c5) i2 = -x5(c1)+x7(c3)-x9(c5) imaginary outputs figure 14. down convert and decimate function using polyphase filters HSP43216
3-13 if external multiplexing is selected ( int/ext = 0), a demultiplex function is required off chip to break the input data stream into even and odd samples for input through ain0-15 and bin0-15. in this mode, the real and imaginary processing legs run at the input clock rate which allows the device to perform the down convert and decimate function on real signals sampled at up to twice the maximum speed grade of the device (104 msps). with external multiplexing, the minimum pipeline delay through the upper processing leg is 9 clks and the pipeline delay through the lower processing leg is 26 clks as shown in figure 15b. to synchronize the even samples input through ain0-15 with the zero degree cosine term of the quadrature lo, sync should be asserted on the same clock that the target sample is present at the input of the part as shown in figure 17. note: for proper operation, the samples demultiplexed to the ain0-15 input must precede those input to the bin0-15 input in sample order. for example, given a data sequence x0, x1, x2, and x3, the demultiplex function would route x0 and x2 to ain0- 15 and x1 and x3 to bin0-15. quadrature to real conversion mode (mode1-0 = 11) the quadrature to real conversion mode is used to construct a real output from a quadrature input. to accomplish this, the halfband filter processor interpolates the quadrature components of the complex input signal by a factor of two. next, the quadrature up-convert processor spectrally shifts the signal by f s /4 and derives the real output as described in the f s /4 quadrature up-convert processor section. the direction of the spectral shift is controlled via the usb/lsb input and is used to designate the frequency content of the complex input as either the upper or lower sideband of the resulting real output signal. a spectral representation of quadrature to real conversion is shown in figure 18 for usb/lsb = 1. note: the f s /4 up-convert processor uses quadrature mix factors scaled by two to compensate for the attenuation introduced by the interpolation process. figure 15a. data flow diagram for down convert and decimate mode ( int/ext = 1) figure 15b. data flow diagram for down convert and decimate mode ( int/ext = 0) even tap filter odd tap filter ain0-15 aout0-15 oea r e g r e g r e g r e g r e g r e g r n d f m t r e g r e g r e g r e g 1,-1,1,-1,... 2 2 bout0-15 oeb r n d f m t r e g r e g -1,1,-1,1,... ? clocked at clk/2 ? ? ? ? ? ? ? group delay 19 ? pipeline delay 2-35 ? group delay 19 ? pipeline delay 19 even tap filter odd tap filter ain0-15 aout0-15 oea r e g r e g r e g r e g r e g r e g r n d f m t r e g r e g r e g r e g 1,-1,1,-1,... 2 2 bout0-15 oeb r n d f m t r e g r e g -1,1,-1,1,... bin0-15 r e g r e g group delay 19 pipeline delay 2-35 group delay 19 pipeline delay 19 0 12 clk sync ain0-15 3 the sample designated by the 0 o and 180 o labels are mixed with the respective cosine terms on the upper processing leg, and the other samples, those labeled by 90 o and 270 o , are mixed with the respective sine terms on the lower leg. figure 16. data synchronization to 0 o phase of quadrature lo 0 o 90 o 180 o 270 o 012 clk sync ain0-15 the 0 o and 180 o labels indicate the phase alignment of the samples input through ain0-15 with the cosine term of the quadrature down convert lo. figure 17. data synchronization with phase of down convert lo 0 o 180 o 180 o 0 o HSP43216
3-14 the quadrature to real conversion mode is most easily understood by first considering an implementation using a 7 tap transversal filter as shown in figure 19. by examining the combination of interpolation, filtering, and up conversion it is seen that a particular output is only dependent on the sum-of-products for the even indexed samples and coefficients or the sum-of-products for the odd indexed samples and coefficients. this computational partitioning allows the dual interpolation filters required in this mode to be realized using the same polyphase filter structure used in the other modes. a functional block diagram of the polyphase implementation for quadrature to real conversion mode is shown in figure 20. in this implementation, the real and imaginary components of a complex input stream drive the even and odd tap filters. the output of each filter is then modulated by the non-zero mix factors and multiplexed into a single real output stream. figure 18. quadrature to real conversion real output upconverted signal filter passband input signal spectrum 0f s /2 f s -f s /2 0 f s /2 f s -f s /2 0f s 2f s -f s f s = input sample rate interpolated signal 0f s /2 f s -f s /2 f s = interpolated sample rate, 2f s c0 c1 c2 c3 c4 c5 c6 0,1,0,-1... -1,0,1,0... halfband filter ..r1,r0 2 ..r1,0,r0,0 c0 c1 c2 c3 c4 c5 c6 ..,y2,y1,y0 ..i1,i0 2 ..i1,0,i0,0 y(0) = 0(0(c0)+r0(c1)+0(c2)+r1(c3)+0(c4)+r2(c5)+0(c6))+ -1(0(c0)+i0(c1)+0(c2)+i1(c3)+0(c4)+i2(c5)+0(c6)) y(1) = 1(r0(c0)+0(c1)+r1(c2)+0(c3)+r2(c4)+0(c5)+r3(c6))+ 0(i0(c0)+0(c1)+i1(c2)+0(c3)+i2(c4)+0(c5)+i3(c6)) y(2) = 0(0(c0)+r1(c1)+0(c2)+r2(c3)+0(c4)+r3(c5)+0(c6))+ 1(0(c0)+i1(c1)+0(c2)+i2(c3)+0(c4)+i3(c5)+0(c6)) y(3) = -1(r1(c0)+0(c1)+r2(c2)+0(c3)+r3(c4)+0(c5)+r4(c6))+ 0(i1(c0)+0(c1)+i2(c2)+0(c3)+i3(c4)+0(c5)+i4(c6)) halfband filter cos(( n +1) /2) sin(-( n +1) /2) + figure 19. quadrature to real converter using transversal filters y(0) = -1(i0(c1)+i1(c3))+i2(c5)) y(1) = 1(r0(c0)+r1(c2)+r2(c4))+r3(c6)) y(2) = 1(i1(c1)+i2(c3)+i3(c5)) y(3) = -1(r1(c0)+r2(c2)+r3(c4)+r4(c6)) c0 c2 c4 c6 c1 c3 c5 r e g odd tap filter even tap filter 1,-1,1,-1,.. -1,1,-1,1.. cos lo sin lo ..r1,r0 ..i1,i0 m u x ..,y2,y1,y0 figure 20. polyphase implementation of quadrature to real converter HSP43216
3-15 as in the other modes, the operation of the HSP43216 in quadrature to real conversion mode is analogous to that of the polyphase solution described above. the data ?w diagrams for this particular mode are shown in figures 21a and 21b. if internal multiplexing is speci?d ( int/ext = 1), the real and imaginary components of the quadrature input are fed through ain0-15 and bin0-15 and processed on the upper and lower legs respectively (see figure 21a). each component of the complex input is interpolated, mixed with the non-zero sine and cosine terms of the quadrature lo, and multiplexed together into a real output sample stream through aout0-15. prior to the output multiplexer, the upper and lower processing legs each run at the input data rate of clk/2 as indicated by the ? ?marking the various registers and processing elements in figure 21a. the complex input sample stream may be synchronized with the zero degree phase of the up converters quadrature lo by asserting the sync control input one cycle prior to the targeted data sample as shown in figure 22. this ensures that the real sample input on the upper processing leg will be mixed with the zero degree cosine term. the minimum pipeline delay through the real processing leg (upper leg) is 15 clks and the delay through the imaginary processing leg (lower leg) is 48 clks. if external multiplexing is selected ( int/ext = 0), output from the upper and lower processing legs exit through aout0-15 and bout0-15 for multiplexing into a single data stream off chip (see figure 21b).this allows the processing legs to run at the maximum clk rate which coincides with an interpolated output data rate of up to 104 msps. note: the output on bout0-15 precedes that on aout0-15 in sample order. this requires a multiplexing scenario which selects bout0-15 then aout0-15 on each clk of the HSP43216. with external multiplexing, the minimum pipeline delay through the upper processing leg is 9 clks and the pipeline delay through the lower processing leg is 26 clks as shown in figure 21b. the sync control input is used as described in the preceding paragraph. ? clock at input data rate, clk/2 figure 21a. data flow diagram for quadrature to real conversion mode ( int/ext = 1) figure 21b. data flow diagram for quadrature to real conversion mode ( int/ext = 0) even tap filter odd tap filter ain0-15 r e g r e g r e g r e g r e g r e g r e g r e g 1 1 2,-2,2,-2,... bin0-15 r e g r e g r e g m u x -2,2,-2,2,... aout0-15 oea r n d f m t r e g r e g ? ? ? ? ? ? ? group delay 19 ? pipeline delay 2-35 ? group delay 19 ? pipeline delay 19 even tap filter odd tap filter ain0-15 r e g r e g r e g r e g r e g r e g r e g r e g 1 1 2,-2,2,-2,... bin0-15 r e g r e g -2,2,-2,2,... aout0-15 oea r n d f m t r e g r e g bout0-15 oeb r n d f m t r e g r e g group delay 19 pipeline delay 2-32 group delay 19 pipeline delay 19 0 clk/2 sync ain0-15 figure 22. data synchronization with processing legs ( int/ext = 1) bin0-15 HSP43216
3-16 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . .gnd -0.5v to v cc +0.5v esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) plcc package. . . . . . . . . . . . . . . . . . . 23.0 n/a mqfp package . . . . . . . . . . . . . . . . . . 35.0 n/a maximum junction temperature plcc and mqfp packages. . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35469 gates caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?ations v cc = 5.0v 5%, t a = 0 o to 70 o c parameter symbol test conditions min max units power supply current i ccop v cc = max, clk frequency 52mhz int/ext = ?? notes 2, 4 - 468 ma v cc = max, clk frequency 52mhz int/ext = ?? notes 3, 4 - 572 ma standby power supply current i ccsb v cc = max, outputs not loaded - 500 a input leakage current i i v cc = max, input = 0v or v cc -10 10 a output leakage current i o v cc = max, input = 0v or v cc -10 10 a clock input high v ihc v cc = max 3.0 - v clock input low v ilc v cc = min - 0.8 v logical one input voltage v ih v cc = max 2.0 - v logical zero input voltage v il v cc = min - 0.8 v logical one output voltage v oh i oh = -3ma, v cc = min 2.6 - v logical zero output voltage v ol i ol = 5ma, v cc = min - 0.4 v input capacitance c in clk frequency 1mhz, all measurements ref- erenced to gnd. t a = 25 o c, note 5 -12pf output capacitance c out -12pf notes: 2. power supply current is proportional to frequency. typical rating is 9ma/mhz when internal multiplexing is selected, int/ext = 1. 3. power supply current is proportional to frequency. typical rating is 11ma/mhz when external multiplexing is selected, int/ext = 0. 4. output load per test circuit and c l = 40pf. 5. not tested, but characterized at initial design and at major process/design changes. 6. maximum junction temperature must be considered when operating part at high clock frequencies. HSP43216
3-17 ac test load circuit note: test head capacitance. ac electrical speci?ations (note 7) parameter symbol notes 52mhz units min max clk period t cp 19 - ns clk high t ch 7-ns clk low t cl 7-ns setup time ain0-15, bin0-15 to clk t ds 7-ns hold time ain0-15, bin0-15 from clk t dh 0-ns mode0-1, rnd0-2, int/ext, sync, usb/lsb setup time to clk t rs 7-ns mode0-1, rnd0-2, int/ext, sync, usb/lsb hold time to clk t rh 0-ns clk to aout0-15, bout0-15 delay t do -9ns output enable time t oe -9ns output disable time t od note 8 - 9 ns output rise, output fall times t r , t f note 8 - 5 ns notes: 7. ac tests performed with c l = 40pf, i ol = 5ma, and i oh = -3ma. input reference level for clk is 2.0v, all other inputs 1.5v. test v ih = 3.0v, v ihc = 4.0v, v il = 0v. 8. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or changes. equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 HSP43216
3-18 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com waveforms figure 23. timing relative to clk figure 24. output rise and fall times clk ain0-15, bin-15 aout0-15, bout0-15 oe t ch t cp t cl t ds t dh t rs t rh t do t od t oe mode0-1, rnd0-2, int/ext, sync, usb/lsb t r t f 0.8v 2.0v HSP43216

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